1. Field
The present disclosure pertains to the field of power management in data processing systems with cache memories.
2. Description of Related Art
One technique for reducing power consumption and heat generation in data processing systems includes reducing the operating frequency of a processor. In many systems, there is a cache memory to support the processor, and, particularly in multiprocessor systems, the cache must be snooped in order to maintain cache coherency. A cache “supports” a processor if the processor normally (e.g., excepting snoop and inquiry accesses) presents memory accesses to cacheable memory space to the cache, or if the cache is a cache at a lower (further from the processor) level in the memory hierarchy that is inclusive with respect to the cache to which the processor normally presents memory accesses to cacheable memory space.
In a system where a processor is supported by a cache that must be snooped to maintain cache coherency, a reduction in the processor's operating frequency may decrease system performance by adding latency to the snoop requests from the system bus.